According to one of the related-art layout design methods of semiconductor integrated circuit such as large scale integration (LSI), a circuit partitioned into a plurality of blocks by function is hierarchically layered and then layout-designed on a per layer basis. Design data are then collected to perform the whole system design.
A crosstalk noise check is typically performed in parallel with the layout design. In a typical method, for example, a layout is designed while a noise check is performed to make sure that no crosstalk noise is generated. All layers are expanded with the layout of the entire semiconductor circuit completed (all the placing and routing completed), and the crosstalk noise check is performed on all the wire lines.
A designer may perform a variety of layout designs to make sure that no crosstalk noise is generated in a layer design phase. For example, line spacing is widened such that no effect is caused by another wire line. For shielding purposes, a ground wire line may be interposed between wire lines presenting a problem.
In another known method, a driving power of an aggressor wire line or a victim wire line is adjusted in the layer layout phase. In yet another method, crosstalk noise is prevented from being generated on a hierarchically high layer by arranging a wiring inhibit area beforehand within a hierarchically low layer.
In addition to the above layout methods, the following methods are also available. In one method, check results of a hierarchically low layer are organized in a library and then added to the check results of a hierarchically high layer in the checking of a net linking the hierarchically low layer to the hierarchically high layer. In another method, lengths of parallel running wire lines in layers are summed. If the sum of the wire lines exceeds a reference line length, an error is suspected, and a crosstalk location is thus identified.
Related arts are described in Japanese Laid-open Patent Publication No. 2005-63275, Japanese Laid-open Patent Publication No. 2002-270775, Japanese Laid-open Patent Publication No. 2003-44540, Japanese Laid-open Patent Publication No. 2001-217315, and Japanese Laid-open Patent Publication No. 2004-185374.
The method of expanding all the layers with the layout of the entire semiconductor circuit completed, and performing the crosstalk noise check on all the wire lines has the problem discussed below. A data size greatly increases as the number of layers increases, and a memory used in a computer is occupied by data of the wire lines. The calculation speed of the computer is reduced.
Even if the crosstalk noise is controlled as much as possible by improving the layout design, the layout of a block at a layer level may remain pending in the layer design. For example, in the layout of a particular block, a driver driving power may remain unknown, a wire line extending to another layer may be present, wire lines in the vicinity of a boundary may include one extending to a driver or a receiver, and the effect of a wire line on an adjacent block is unknown. In such a case, the crosstalk noise is difficult to check correctly.
The method of widening the line spacing and the shielding method of interposing the ground wire line between the problematic wire lines are also associated with an inefficient layout problem such as an introduction of a dead space in the semiconductor circuit and an increase in a die size.
The layout constraint is imposed as described above to perform the crosstalk noise check correctly, and the crosstalk noise is also reduced. Such a method has a limited effect in current LSIs.
The check results of the hierarchically low layer are organized in the library and then added to the check results of the hierarchically high layer. With this method, however, the checking of the crosstalk noise is difficult because a wire line passing above and a wire line adjacent to a boundary in the hierarchically low layer are not accounted for.
In the method, the lengths of parallel running wire lines in layers are summed. If the sum of the wire lines exceeds a reference line length, an error is suspected, and a crosstalk location is identified. The summing of the lengths of the parallel running wire lines alone leads no correct crosstalk noise check. The checking of the crosstalk noise is difficult because the wire line passing above the low layer and the wire line adjacent to the boundary in the hierarchically low layer are not accounted for. With this method, the crosstalk noise check is not correctly performed.